1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device. More particularly, the present invention relates to a method for reading the non-volatile semiconductor memory device, a method for setting a state of a reference cell, and a circuit for reading the non-volatile semiconductor memory device.
2. Description of the Background Art
Non-volatile semiconductor memory devices are capable of holding data after turning OFF a power source, and therefore, are widely used in information systems, communication systems and the like. Flash EEPROM is a type of non-volatile semiconductor memory device, from which data can be erased for an entire chip or only on a block-by-block basis where the block has a predetermined size. The flash EEPROM has a small memory cell size and low manufacturing cost, so that its demand is rapidly increasing.
A binary flash EEPROM controls the thresholds of memory cell transistors to store one-bit data in each memory cell. More specifically, the threshold of the memory cell transistor is controlled to be in different states so that a memory cell current when data “0” is stored is distinguished from a memory cell current when data “1” is stored. An intermediate current value between the memory cell current when data “0” is stored and the memory cell current when data “1” is stored is previously set as a read reference. By comparing a memory cell current during a read operation with the previously set read reference, it is determined whether read data is “0” or “1”.
FIG. 28 is a diagram illustrating a distribution of a memory cell current in the binary flash EEPROM. In the binary flash EEPROM, each memory cell is set to be in one of two states (hereinafter referred to as a first state and a second state). A memory cell current in the first state and a memory cell current in the second state each have a distribution around a predetermined value as a center. A read reference IR is set to be somewhere in a range in which the two memory cell current distributions do not overlap (in FIG. 28, a range IW; hereinafter referred to as a read window), for example, the center of the read window. During a read operation, a memory cell current is compared with the read reference IR. When the memory cell current is smaller than the read reference IR, data is determined to be “1”. Otherwise, read data is determined to be “0”.
When a read operation is performed in the above-described method, it is desirable that the read reference is set to be at the center of the read window with high accuracy. However, the read reference is different from both the memory cell current in the first state and the memory cell current in the second state, and therefore, the read reference needs to be generated using a certain method. To generate the read reference, various methods have been used: a method based on a voltage generated by a reference voltage generation circuit; a method employing a transistor having a size or a structure different from that of an ordinary memory cell; a method of performing a write operation with respect to a memory cell which is composed of a transistor which is the same as that of an ordinary memory cell, in a manner different from that of the ordinary memory cell; and the like. However, it is difficult to set the read reference IR to be a desired value with high accuracy using any of these methods. Therefore, in order to broaden the width of the read window, measures are taken, such as setting the threshold of a write memory cell to be high, and the like.
In the above-described conventional reading methods using a read reference, it is necessary to set a sufficient margin between a memory cell current in each state and a read reference, taking into consideration variations in characteristics of memory cells during a manufacturing process, a difference in characteristics between a memory cell and a read reference generation circuit (a difference in voltage characteristics or temperature characteristics), a change over time in characteristics of a memory cell (a change in characteristics depending on the number of times of a write operation or an accumulated operating time), and the like. Therefore, in order to achieve a low voltage operation, a charge pump circuit is required which provides a voltage higher than a power source voltage to the control gate of a memory cell during a read operation. However, when the charge pump circuit is provided, an operating current increases.
Japanese Patent Laid-Open Publication No. 2001-67887 of the present inventors discloses a method for solving the above-described problems. According to this method, as illustrated in FIG. 29, an average value of a memory cell current in the first state is used as a first read reference REF1, and an average value of a memory cell current in the second state is used as a second read reference REF2. During a read operation, the degree of match between a memory cell current and the first read reference REF1 and the degree of match between the memory cell current and the second read reference REF2 are calculated. It is determined whether read data is “0” or “1”, depending on which of the two degrees of match is higher than the other.
Thus, by using the average value of a memory cell current in each state as a read reference, the read reference can change, following the characteristics of the memory cell even when there are variations in characteristics of memory cells during a manufacturing process or a change in characteristics in an operating environment. Therefore, data can be read out with high accuracy, and a setting margin of a read reference and a fluctuation margin of characteristics can be reduced.
The above-described publication also discloses a semiconductor memory device in which, when a rewrite operation is performed with respect to a memory cell, a rewrite operation is also performed with respect to a memory cell which generates a read reference. In this semiconductor memory device, when characteristics of a memory cell are changed due to the rewrite operation, the read reference is also changed in association with this. Therefore, data can be read stably even when there are variations in characteristics of memory cells during a manufacturing process, a difference in characteristics between an ordinary memory cell and a memory cell for generating a read reference, a change over time in characteristics of a memory cell, or the like.
The state of a memory cell contained in a flash EEPROM is changed due to erase and write operations. Variations occur in the erase characteristics and the write characteristics of a memory cell contained in a flash EEPROM due to variations in memory cells during a manufacturing process, variations in power source voltage in a memory cell array, or the like. Also, the mutual conductance of a memory cell transistor varies, so that a memory cell current varies even when the threshold of the memory cell transistor is the same.
In the flash EEPROM, an erase operation is performed for an entire memory cell array or on a block-by-block basis where the memory cell array is divided into a plurality of blocks. In the latter case, an erase operation is performed equally for all memory cells in a block to be erased until they all pass through erase verification. Therefore, if there are variations in erase characteristics of memory cells in the block, variations also occur in the thresholds of memory cell transistors after an erase operation.
In contrast, in the flash EEPROM, a write operation is performed in units of several bits to several K bits which are called a word or a page. In this case, write verification is performed on a memory cell-by-memory cell basis, and a write operation with respect to a memory cell is controlled on a bit-by-bit basis. Therefore, a memory cell current after an erase operation is distributed in a wider range than that of a memory cell current after a write operation (see FIG. 30). Therefore, when an average value of a memory cell current after a write operation is represented by a first read reference REF1 and an average value of a memory cell current after an erase operation is represented by a second read reference REF2, the average value (REF1+REF2)/2 is not located at the center of the read window. Therefore, optimum read conditions are not necessarily obtained when an average value of memory cell currents in the states is used as a read reference.